My digital IC learning route

Li Ruifeng 2021-09-15 10:02:52

Many friends, like me, are from FPGA Transfer to number IC, So for numbers IC A lot of knowledge is not very clear , I don't know either , I want to put my number IC The learning route is recorded here , No blog in the whole network can summarize this route in such detail and share it , This blogger hopes to open a first , It is convenient for you to consult and share with your fellow Chinese in the future . in addition , Knowledge also needs to be consolidated . Often look back , To deepen the understanding of knowledge , Of course, I don't write down everything I understand , Because some need you to explore , Sentiment , Just belong to yourself . It's just a journey , experience , Study IC Not a day or two , A few months . In particular, online video resources are fuzzy 、 All kinds of resources are in English , But I don't think we should retreat under these restrictions , Even nothing should be an excuse to stop , And lab It's not as smooth as the Internet , It takes more patience , And wait for , As long as you have a heart that doesn't give up IC The heart of , Will gradually break through , I don't know where to look , Where there is no tutoring , Simply speaking , For example, someone starts with makefile Documents or tcl The document is difficult , Be patient , For example, I have actually seen some videos at different time nodes 5 All over ~, But when we really get to the back , You can catch some details , Understand the meaning of the video , In addition, my following blog posts are not written in order , Instead, build branches in modules , Then each branch keeps moving forward . As I continue to deepen my knowledge , This blog is constantly updated , And may delete some articles with low gold content , And some suggestions that are not very good before and now . Other companies train Lab feeling , For personal records only , No public announcement . Some personal perception articles , Interested in , Readers can study by themselves according to the title , Hold off , Every article is cost Bloggers spend a lot of time copyright , Do not copy or reprint

1、 Get ready to get started IC Global concept series

1.1 Get ready to get started IC Global concept series - On

1.2 Get ready to get started IC Global concept series - in

1.3 Get ready to get started IC Global concept series - Next

2、 Preparation

2.1 ubuntu18.04 install VCS+verdi Error collection

2.2 Article, understand Linux Basic operation ( On )

2.3 Article, understand Linux Basic operation ( Next )

2.4 An in-depth understanding of Linux( Practical )

2.5 Article, understand VIM Basic operation

2.6 Add a memory module , Speed up your notebook

2.7 samsung SSD T5 loading ubuntu Take it with you, plug and play

3、 Start to understand digital circuits and Verilog Well

3.1 A new understanding of Verilog

4、IC Tool usage -VCS

4.1 IC- Tools section –VCS Use the tutorial - Volume one (20200328)

4.1 Add VCS Official guide reading notes

4.2 IC- Tools section –VCS Use the tutorial - Volume one (20200413)

4.1 VCS-bilibili Tutorial 1-Simulation Basics

4.2 VCS-bilibili Tutorial 2-Debug Basic

5-1、IC Tool usage -DC

5.1 DC Using the tutorial series 1-.synopsys.dc.setup The establishment of the

5.2 DC Using the tutorial series 2- Concept of clock and constraint script

5.3 DC Use the tutorial -command( Continuous updating )

5-2 、IC Tools bilibili Video tutorial -DC

5.1 DC Course notes - Digital logic synthesis tool -DC Environment Attributes

5.2 DC Course notes - Digital logic synthesis tool -DC Synthesis Optimization Techniques

5-3 、IC Tool use -DC official workshop piece

5.1 DC workshop Guidance chapter 1- Setup and Synthesis Flow

6-1、DFT Video series Concept


6.3 DFT command

6-2 、DFT Training course notes -bilibili edition

6.1 DFT Training course notes 1(bibili edition )- introduction to DFT& DFT Architecture

6.2 DFT Training course notes 2(bibili edition )- Scan synthesis practice

6.3 DFT Training course notes 3(bibili edition )-SOC Scan Implementtation( The second half will be seen later )

6.4 DFT Training course notes 4(bibili edition )- ATPG(137 You need to look at it later D Algorithms and other theories )

6.5 DFT Training course notes 5(bibili edition )- ATPG Practice&ATPG Practice II (93 after lab use mentor , Not yet )

6-3、 About DFT Thinking about relevant issues

6.2.3、 How to really understand DFT Some concepts and ideas ?

6-4、DFT ug Reading notes

DFTug -Getting Started (DFT basic flow) - Part 1

DFTug -Getting Started (DFT basic flow) - The next part

DFTug - Architecture Your Test Design

DFTug - Architecture Test Clocks

DFTug - Introduction to Test Models

DFTug - Test_point

DFTug - Pipelined Scan Data

DFTug - change_names With Verilog Rule

DFTug - Scandef

DFTug - OCC support

DFTug - Configuring Clock-Gating Cells(ICG)

-----ATPG Troubleshooting------
S1 violation - Troubleshooting a Scan Chain Blockage

6-5 、DFT axr Theory and practice video tutorial notes

6-5.1 Scan Chain Principle and implementation of ( theory )

6-5.2 Scan Chain Principle and implementation of ( practice ) - TOP Down Flow( On )

6-5.3 Scan Chain Principle and implementation of ( practice ) - TOP Down Flow( Next )

7、Training Thoughts

7.1 Memory Test Concept and Flow Lab ( not public )

7.2 DFT-TDS Flow( not public )

7.3 Review DFT Lab1 training ( not public )

8、 In the work Linux Skill supplement

Linux Tips on how to display the number of files & Compare whether the two folders are the same

Powerful grep Command to use

9、Design for Test Read and think

9.1 Why do it scan extraction?

9.2 In depth understanding of Scan_replacement

10、Tmax ATPG ug series

IEEE STIL File syntax summary

TMAXug - getting start

TMAXug ATPG Design Flow

11、Verdi piece

11.1 Verdi GUI Skill operation Before you start

11.2 Verdi GUI Skill operation -nwave part

11.3 Verdi GUI Skill operation -nschema part

11.4 Verdi GUI Skill operation -Application Tutorials part

11.5 Verdi .rc operation ( not public )

11.6 Verdi And TCL Script ( not public )

12、TCL Basic introductory grammar

12.1 TCL Basic grammar

13、IC Front end design series (bilibili edition )

13.1 DC Theory and practice of 【task 9、10】

14、DFT project Practical training experience ( Keep it confidential )

About block_setting The doubts inside

XX33 project (2021/2 month -2021/5 month ):

DFT projectXX44 Project experience summary 1

DFT projectXX44 Time flow notes

XX44 project bug Summary of experience

XX39 project bug Summary of experience

XX39 project FINAL summary

15、project experience

Information to be seen & Questions

DFT sign-in Form

XX30 scan plan

XX30:block - otp_top

obtain netlist The way to do it and co-work matters needing attention

16、 Work piece ( Most of the secrets are not public )

Information and questions to be seen

Slide Production skills

Chat record

Linux Quick use of work experience ( Open : Continuous updating )

VIM Practical work skills

About verdi Needs and skills to use ( Open : Continuous updating )

Company structure and industry news

Import verdi Of symbol library

At work FLOW Notice in INT&mail&qrsh&

scan Set error prone points

chip Set error prone points

IC co-work mail Flow

workcareer DFT Key experience ( not public )

make it - How to deal with it 1‘b0 and 1‘b1

Understand all report file

How to view the current pattern Whether the environment has measured what fault?( not public )

How to view the current instance How much or what is covered faults

How to improve Scan Test Coverage to An Acceptable Level

Why does it happen normally pattern Of SE The signal doesn't pull down every time ?

Why? dump waveform When serial At least set to 2 above

How to understand c39 violation?

PSD - Debugging Parallel Simulation Failures for Combined Pattern Validation(CPV)

verification STIL Of pattern The input order of

verification force_PI&measure_po Is there any realization

Why? netlist post Then we need to run ATPG?

Why open SDFF/Q And test_mode phase & The function of ?

how to achive scan_replacement during scan insertion?

Error: can‘t find OCC toggle in patterns!

According to all OCC drive Of faults_list Extract the specified OCC Measured AN

Auto Latch Insertion Flow

verification insert lockuplatch at pipehead/pipetail

Explore in compression Under the architecture lockup Where to insert

checklist Mechanism

Why? scan_clk And function_clk Can't share

Why not recommend Zhengyan +lockup+ Negative edge scan chain?

Thoroughly understand ICG The basic concept of

DFTug - Configuring Clock-Gating Cells(ICG)

pindata =load The meaning of

Modify inout port

PAD Change it to buf It's efficient style

ATE On board test co_work

sub_module Add wrapper promote testcov

Appoint DFT logic insertion The location of (DFT Logic insertion Location)

SPC(shift power control) Basic knowledge of

DFTC And TMAX Different cognition - clock edge Cognitive differences & function aware insertion

read_faults XX.list -force_retain_code The role of

Use SNPS TCL Quickly modify D1/D3 violation To verify ATPG

Netlist/SPF matching for ATPG Instructions for use

SAF coverage improvement to Target Practical project experience

SAF coverage improvement to Target Practical project experience 2

ATPG Faults Classification depth analysis

intl pattern count Limit and reduce test time

LIB cell Summary of naming and combinatorial logical relationships

How to generate OCC_info Relevant information and precautions

17 、ATPG DRC Depth study ( Not for the time being )

ATPG Z Series error Tristate rules

ATPG S Series error Scan Chain Rules

ATPG C Series error clock rules

ATPG B Series error build model

strange Error series

18 、advaned DFT Techology( Keep it confidential )

DFT Advanced processing method and implementation – stay com framework insert_dft When to disable certain cell

DFT Advanced processing method and implementation – classify port or cell

DFT Advanced processing method and implementation – Yes PIPO The handling of makes cov promote

DFT Advanced processing method and implementation – Yes PIPO The handling of makes cov promote 2

19 、 Learn a little on weekends TCL series ( Open )

TCL incr Meaning and usage

TCL foreach Usage of

TCL proc Usage of

TCL with SNPS - collection

TCL with SNPS - get_object_name&sizeof_collection&string

TCL with SNPS info exists&create_cell&create_net&connect_net

TCL with SNPS sizeof_collection&get_object_name&find&get_libs&list_attributes

TCL with SNPS collection_limit&get_lib_pins

TCL with SNPS get_attribute&get_lib_attribute&list_attributs&report_attribute

TCL with SNPS llength&lappend&get_cells

TCL with SNPS file exists&file rename/copy & redirect & lsearch & split


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