title: DMA Design

tags: linux

date: 2019 year 1 month 5 Japan 17:27:08

toc: true

DMA Design

DMA frame

A simple DMA The block diagram is as follows DREQ→HOLD→HLDA→DACK

DMAC Some of the essential features of :

  • Can send address information , Addressing memory , And modify the address pointer ,DMAC There must be an internal device that can automatically add 1 Or minus 1 The address of
  • Can determine the number of bytes transmitted , And can judge DMA Is the transmission over .DMA There has to be something inside that can automatically reduce 1 Word count register for , The end of the count produces a stop count signal ;
  • Can send out DMA End signal , Release the bus , send CPU Restore bus control ;
  • Can send out read 、 Write control signals , Including memory access signals and I/O Access signals .DMAC There must be internal timing and read-write control logic .

The signal line is as follows

  • DRQ:DMA Request signal . It's peripherals DMA The controller requests DMA Application signal for operation .
  • DACK:DMA response signal . yes DMA The controller proposes to DMA The peripheral of the request indicates that the request has been received and is being processed .
  • HOLD: Bus request signal . yes DMA Controller to CPU A request signal to clear the bus .
  • HLDA: Bus response signal , yes CPU towards DMA The controller represents a reply signal that allows bus requests .

Process sequence

  1. There's DMA demand , And ready , As to the DMAC The controller sends out DMA Request signal DREQ
  2. DMAC Receive DMA Request signal backward CPU Send a bus request signal HRQ. The signal is connected to CPU Of HOLD The signal .
  3. CPU After receiving the bus request signal , If allowed DMA transmission , After the end of the current bus cycle , issue DMA response signal HLDA. One side CPU Will control the bus 、 Data bus and address bus are in high resistance state , That is to give up control of the bus ; On the other hand CPU Will be effective HLDA The signal is sent to DMAC, notice DMAC,CPU Has given up control of the bus .
  4. DMAC Gain control of the bus , And send out DMAC The answer signal of DACK, Notify peripherals to start DMA Transmitted .
  5. DMAC Send address signal to memory and send read signal to memory and peripheral / Write control signals , The control data is transmitted according to the initialization direction , Realize data transmission between peripheral and memory .
  6. After all the data is transferred ,DMAC towards CPU Hair HOLD The signal , Request to cancel bus request signal .CPU After receiving the signal , send HLDA Invalid , And take back control of the bus .

DMA The basic composition of the controller

  • Memory address counter : The address used to store the data to be exchanged in memory .
  • Word counter : Used to record the length of the transfer block ( How many words ).
  • Data buffer register : It is used to store the data of each transmission ( One word ).
  • "DMA request " sign : Every time the device prepares a data word, it gives a control signal , send "DMA request " Mark place "1". The flag is set backward " control / state " Logic sends out DMA request , The latter goes to CPU Issue a request for bus access (HOLD),CPU Send back a response signal in response to this request HLDA," control / state " The logic receives this signal and sends out DMA response signal , send "DMA request " Flag reset , Ready to swap the next word .
  • " control / state " Logic : It is composed of control and sequential circuits and state marks , Used to modify the memory address counter and word counter , Specify the delivery type ( Input or output ), Also on "DMA request " Signals and CPU Coordinate and synchronize in response to signals .
  • Interruption mechanism : When the word counter overflows , It means that a set of data has been exchanged , The interrupt mechanism is triggered by the overflow signal , towards CPU Report the interruption .

Please see the English manual

Chip characteristics

Source of the request

  • Software triggers

  • Peripheral trigger

  • External pins trigger , This is STM32 Not available , This has a specific time sequence ,STM32 It should be triggered by interrupt pin

2440 Channel transmission type

  • The source and target are on the system bus ( such as : Two physical memory addresses )
  • When the target is on the peripheral bus , The source is on the system bus ( Peripherals refer to : A serial port , Timer ,I2C,I2S etc. )
  • When the target is on the system bus , The source is on the peripheral bus
  • The source and destination are on the peripheral bus ---------- This ST I don't have

External pin's DMA agreement

This seems a little complicated , I haven't used it yet , Don't do in-depth analysis for the time being

Brief description of the agreement

2440 Inside DMA There are two levels of transmission , One is REQ/ACK agreement , The other is single mode and full mode , The so-called single mode and full mode refers to the single mode DMA The number of transfers in the request

Basic timing

Timing parameters

  • The validity of the signal : High level invalid , Low level active , This is called assert

  • REQ It works

    REQ It's only in the ACK Release (high) It's only when you're in love that you can be asserted(high), in other words Request signals can only be sent in ACK Only when it is high can it be MCU Of DMA Identify to

  • Signal validation identification

    nXDREQ The request came into effect and passed 2CLK After cycle synchronization ,nXDACK Respond and take effect , But at least we have to go through 3CLK Cycle delay of ,DMA The controller can get control of the bus , And start data transmission .

Pattern

  • Single service : When there is no atomic transport (unit/burst) after , Stop transmitting , Wait for the next request

  • Whole service : Repeat atom transfer , Until the counter reaches 0. In this mode , No need for another request . This is the point

    In full mode ,DMA It also releases the bus after each atom is transferred and then tries to get the bus , To prevent the bus from being occupied

in other words , The full pattern is the pattern we usually use , Use counter , One request transfers all the data . Single mode transfers one atomic operation at a time .

ACK Zero clearing :

  • A single service is an atomic operation
  • Full service is to complete all transfers

Interruption occurs :

  • All in the counter for 0 When

agreement

The agreement here , The request response protocol , Divided into two .

  • Demand Mode request / Query mode

    If REQ Signal valid , Then keep transmitting all the time , At this time ACK Just to tell you that this transmission is complete

    This mode will take over the bus , It's not like doing an atomic operation in a full service to release the bus

  • Handshake Mode Handshake mode

    If REQ Signal release , This is the time DMA The controller releases ACK Two cycles , otherwise DMA Will wait until REQ Release

    That is, before starting the next transmission , The requester needs to release first , then MCU When it's done, it doesn't work ACK Two cycles tell the requester , The requester requests again , Otherwise, we will wait

stay Demond In mode , If DMA After completing a request, if Request Still valid , that DMA Think this is the next time DMA request , And immediately start the next transmission ;

stay Handshake In mode ,DMA Wait after completing a request Request Invalid signal , If Request Invalid ,DMA It will be invalid ACK Two clock cycles , Wait for the next time Request.

Description of data size

The size of the data transfer = Number of data transfers * Number of reads and writes per transfer * The size of a read or write

  • The number of reads and writes per transmission can be 1 A or 4 individual unit/burst
  • The size of a single read or write can be 1 byte ,2 byte ,4 byte

Concrete and complete instance sequence

Single service query request mode

Single service handshake mode

Full service handshake mode

It doesn't really matter here hand 了 , Because in full mode, only one request is needed to complete all subsequent operations

Code design

The code here is to drive a copy of memory , It doesn't involve the time series analysis mentioned above , Just need to set the relevant register configuration DMA The pattern of , Then start DMA Later into dormancy , After completion DMA Interrupt wake up and exit .

The test program calls the character driver interface ioctl To test

Before writing a program, you need to check what you need DMA

cat /proc/interrupts

The driver

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/arch/regs-gpio.h>
#include <asm/hardware.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <linux/dma-mapping.h> #define S3C_DMA_SIZE 512*1024 //DMA Transmission length 512KB #define NORMAL_COPY 0 // A normal copy between two addresses
#define DMA_COPY 1 // Between two addresses DMA Copy /* Function declaration */
static DECLARE_WAIT_QUEUE_HEAD(s3c_dma_queue); // Declare the waiting queue
static int s3c_dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long flags); /*
* Define the interrupt event flag
* 0: Enter the waiting queue 1: Exit the waiting queue
*/
static int s3c_dma_even=0; static unsigned char *source_virt; // Source virtual address
static unsigned int source_phys; // Source physical address static unsigned char *dest_virt; // Destination virtual address
static unsigned int dest_phys; // Destination virtual address /*DMA3 register */
struct S3c_dma3_regs{
unsigned int disrc3 ; //0x4b0000c0
unsigned int disrcc3 ;
unsigned int didst3 ;
unsigned int didstc3 ;
unsigned int dcon3 ;
unsigned int dstat3 ;
unsigned int dcsrc3 ;
unsigned int dcdst3 ;
unsigned int dmasktrig3; //0x4b0000e0
}; static volatile struct S3c_dma3_regs *s3c_dma3_regs; /* Character device operation */
static struct file_operations s3c_dma_fops={
.owner = THIS_MODULE,
.ioctl = s3c_dma_ioctl,
}; /* Interrupt service function */
static irqreturn_t s3c_dma_irq (int irq, void *dev_id)
{
s3c_dma_even=1; // Exit the waiting queue
wake_up_interruptible(&s3c_dma_queue); // Wake up the interrupt
return IRQ_HANDLED;
} /*ioctl function */
static int s3c_dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long flags)
{
int i;
memset(source_virt, 0xAA, S3C_DMA_SIZE);
memset(dest_virt, 0x55, S3C_DMA_SIZE); switch(cmd)
{
case NORMAL_COPY: // Normal copy for(i=0;i<S3C_DMA_SIZE;i++)
dest_virt[i] = source_virt[i]; if(memcmp(dest_virt, source_virt, S3C_DMA_SIZE)==0)
{
printk("NORMAL_COPY OK\n");
return 0;
}
else
{
printk("NORMAL_COPY ERROR\n");
return -EAGAIN;
} case DMA_COPY: //DMA Copy s3c_dma_even=0; // Enter the waiting queue /* Set up DMA register , Start once DMA transmission */
/* The physical address of the source */
s3c_dma3_regs->disrc3 = source_phys;
/* The source is located in AHB Bus , Source address increment */
s3c_dma3_regs->disrcc3 = (0<<1) | (0<<0);
/* The physical address of the destination */
s3c_dma3_regs->didst3 = dest_phys;
/* The purpose is to AHB Bus , Destination address increment */
s3c_dma3_regs->didstc3 = (0<<2) | (0<<1) | (0<<0);
/* To interrupt , Single transmission , Software triggers , */
s3c_dma3_regs->dcon3=(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(0<<20)|(S3C_DMA_SIZE<<0);
// Start once DMA transmission
s3c_dma3_regs->dmasktrig3 = (1<<1) | (1<<0); wait_event_interruptible(s3c_dma_queue, s3c_dma_even); // Go to sleep , wait for DMA When the transmission is interrupted, it exits if(memcmp(dest_virt, source_virt, S3C_DMA_SIZE)==0)
{
printk("DMA_COPY OK\n");
return 0;
}
else
{
printk("DMA_COPY ERROR\n");
return -EAGAIN;
} break;
}
return 0;
} static unsigned int major;
static struct class *cls;
static int s3c_dma_init(void)
{
/*1.1 register DMA3 interrupt */
if(request_irq(IRQ_DMA3, s3c_dma_irq,NULL, "s3c_dma",1))
{
printk("Can't request_irq \"IRQ_DMA3\"!!!\n ");
return -EBUSY;
} /*1.2 Allocate two DMA buffer ( Source 、 Purpose )*/
source_virt=dma_alloc_writecombine(NULL,S3C_DMA_SIZE, &source_phys, GFP_KERNEL);
if(source_virt==NULL)
{
printk("Can't dma_alloc \n ");
return -ENOMEM;
} dest_virt=dma_alloc_writecombine(NULL,S3C_DMA_SIZE, &dest_phys, GFP_KERNEL);
if(dest_virt==NULL)
{
printk("Can't dma_alloc \n ");
return -ENOMEM;
} /*2. Register character device , And provides a collection of file operations fops*/
major=register_chrdev(0, "s3c_dma",&s3c_dma_fops);
cls= class_create(THIS_MODULE, "s3c_dma");
class_device_create(cls, NULL,MKDEV(major,0), NULL, "s3c_dma"); s3c_dma3_regs=ioremap(0x4b0000c0, sizeof(struct S3c_dma3_regs)); return 0;
} static void s3c_dma_exit(void)
{
iounmap(s3c_dma3_regs); class_device_destroy(cls, MKDEV(major,0));
class_destroy(cls); dma_free_writecombine(NULL, S3C_DMA_SIZE, dest_virt, dest_phys);
dma_free_writecombine(NULL, S3C_DMA_SIZE, source_virt, source_phys); free_irq(IRQ_DMA3, 1); }
module_init(s3c_dma_init);
module_exit(s3c_dma_exit);
MODULE_LICENSE("GPL");

The test program

#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <string.h> /* ./dma_test NORMAL
* ./dma_test DMA
*/
#define NORMAL_COPY 0 // A normal copy between two addresses
#define DMA_COPY 1 // Between two addresses DMA Copy void print_usage(char *name)
{
printf("Usage:\n");
printf("%s <NORMAL | DMA>\n", name);
} int main(int argc, char **argv)
{
int fd,i=30; if (argc != 2)
{
print_usage(argv[0]);
return -1;
} fd = open("/dev/s3c_dma", O_RDWR);
if (fd < 0)
{
printf("can't open /dev/s3c_dma\n");
return -1;
} if (strcmp(argv[1], "NORMAL") == 0)
{
while (i--) // Call driven ioctl(),30 Time
{
ioctl(fd, NORMAL_COPY);
}
}
else if (strcmp(argv[1], "DMA") == 0)
{
while (i--) // Call driven ioctl(),30 Time
{
ioctl(fd, DMA_COPY);
}
}
else
{
print_usage(argv[0]);
return -1;
}
return 0;
}

test

  1. ./dma_test NORMAL & Get stuck
  2. ./dma_test DMA &, Input command response

Reference link

csdn DMA frame

cnblog DMA Request response protocol

cnblog note

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